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Lattice Semiconductor
1GbE PCS IP Core User’s Guide
Introduction
The 1GbE PCS Intellectual Property (IP) Core targets the programmable array section of the ORCA ? ORT42G5
device and provides the PCS (Physical Coding Sublayer) function.
PCS (Physical Coding Sublayer) and PMA (Physical Media Attachment) are sublayers of the physical layer imple-
mentation of IEEE 802.3 standards. The PCS provides a uniform interface to the MAC sublayer through GMII
(Gigabit Media Independent Interface) for all 1000Mb/s PHY implementations.
The ORT42G5 device is built on the Series 4 re-con?gurable embedded System-on-a-Chip (SoC) architecture and
is made up of SERDES transceivers containing four channels, each operating at up to 3.7Gbits/s, with a full-duplex
synchronous interface with built-in RX Clock and Data Recovery (CDR), and transmitter pre-emphasis, for high-
speed data transmission.
This user’s guide explains the functionality of the 1GbE PCS core and how to achieve the maximum level of perfor-
mance.
The 1GbE PCS core comes with the documentation and the ?les listed below:
? Data sheet
? Lattice gate level netlist
? Simulation models and test benches available for free evaluation
? Core instantiation template
Features
? Complete 1Gb Ethernet Physical Coding Sublayer solution based on the ORCA ORT42G5 device
? IP targeted to the ORT42G5 programmable array section implements functionality conforming to IEEE 803.2-
2002
– Encoding/decoding of GMII data octets
– Optional Auto-negotiation function with management registers and interface
– 10Gbps aggregate throughput
? Ethernet functionality supported by the embedded section of the ORT42G5
– Supports 8b/10b encoding/decoding
– Serialization/deserialization of code groups for transmit/receive
– Clock recovery from encoded data stream
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